Paper detail

Conductance of a SET with a retarded dielectric layer in the gate capacitor

We study conductance of a single electron transistor (SET) with a ferroelectric (or dielectric) layer placed in the gate capacitor. We assume that ferroelectric (FE) has a retarded response with arbitrary relaxation time. We show that in the case of "fast" but still retarded response of the FE (dielectric) layer an additional contribution to the Coulomb blockade effect appears leading to the suppression of the SET conductance. We take into account fluctuations of the FE (dielectric) polarization using Monte-Carlo simulations. For "fast" FE these fluctuations partially suppress the additional Coulomb blockade effect. Using Monte-Carlo simulations we study the transition from "fast" to "slow" FE. For high temperatures the peak value of the SET conductance is almost independent of the FE relaxation time. For temperatures close to the FE Curie temperature the conductance peak value non-monotonically depends on the FE relaxation time. A maximum appears when the FE relaxation time is of the order of the SET discharging time. Below the Curie point the conductance peak value decreases with increasing the FE relaxation time. The conductance shows the hysteresis behavior for any FE relaxation time at temperatures below the FE transition point. We show that conductance hysteresis is robust against FE internal fluctuations.