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Source author record

Wilfried Haensch

Wilfried Haensch appears in the imported research catalog. Authorship, coauthor and topic links are available while profile ownership is still unclaimed.

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cond-mat.mes-hallcond-mat.mtrl-sciEmerging TechnologiesArtificial Intelligenceeess.SYHardware ArchitectureMachine LearningNeural and Evolutionary Computingphysics.opticsSystems and Control

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Published work

11 published item(s)

preprint2026arXiv

A3D: Agentic AI flow for autonomous Accelerator Design

Accelerating applications through the design of hardware accelerators can significantly enhance system performance and energy efficiency. Despite advances, such as high-level synthesis (HLS), designing accelerators for complex applications still remains highly labor-intensive, demanding considerable expertise in understanding workloads to be accelerated, hardware design, micro-architecture, and EDA tool usage, posing challenges for application domain experts. Therefore, most accelerator solutions are limited to applications with a regular predictable dataflow. Advances in AI have enabled agents that perform autonomous planning, reasoning, execution and reflection, leading to unprecedented potential for automation through agentic AI. We present A3D, an Agentic AI flow for end-to-end Automation of hardware Accelerator Design. A3D automates workload analysis, performance bottleneck identification, code refactoring for HLS compatibility and micro-architecture generation. A3D also generates diverse accelerator designs by automatically exploring the speed-area tradeoff space. Recent efforts have explored the use of AI for specific tasks such as design space exploration in HLS, leaving several tasks to still be performed manually. A3D addresses the challenges in applying modern LLMs to accelerator design by judiciously partitioning tasks among specialist agents, orchestrating process loops with specialist and verifier agents, utilizing pre-existing and custom tools, and employing agentic RAG for codebase and proprietary EDA tool documentation exploration. Our implementation of A3D, using commercial components like Claude Sonnet 4.5 and the Catapult HLS tool, demonstrates its effectiveness by generating accelerator designs with no human intervention from complex scientific applications like LAMMPS (molecular dynamics simulation) and QMCPACK (quantum chemistry).

0 citations0 reviewsNo code linkedOpen access
preprint2022arXiv

A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks

Deep Learning neural networks are pervasive, but traditional computer architectures are reaching the limits of being able to efficiently execute them for the large workloads of today. They are limited by the von Neumann bottleneck: the high cost in energy and latency incurred in moving data between memory and the compute engine. Today, special CMOS designs address this bottleneck. The next generation of computing hardware will need to eliminate or dramatically mitigate this bottleneck. We discuss how compute-in-memory can play an important part in this development. Here, a non-volatile memory based cross-bar architecture forms the heart of an engine that uses an analog process to parallelize the matrix vector multiplication operation, repeatedly used in all neural network workloads. The cross-bar architecture, at times referred to as a neuromorphic approach, can be a key hardware element in future computing machines. In the first part of this review we take a co-design view of the design constraints and the demands it places on the new materials and memory devices that anchor the cross-bar architecture. In the second part, we review what is knows about the different new non-volatile memory materials and devices suited for compute in-memory, and discuss the outlook and challenges.

0 citations0 reviewsNo code linkedOpen access
preprint2022arXiv

Neural Network Training with Asymmetric Crosspoint Elements

Analog crossbar arrays comprising programmable nonvolatile resistors are under intense investigation for acceleration of deep neural network training. However, the ubiquitous asymmetric conductance modulation of practical resistive devices critically degrades the classification performance of networks trained with conventional algorithms. Here, we describe and experimentally demonstrate an alternative fully-parallel training algorithm: Stochastic Hamiltonian Descent. Instead of conventionally tuning weights in the direction of the error function gradient, this method programs the network parameters to successfully minimize the total energy (Hamiltonian) of the system that incorporates the effects of device asymmetry. We provide critical intuition on why device asymmetry is fundamentally incompatible with conventional training algorithms and how the new approach exploits it as a useful feature instead. Our technique enables immediate realization of analog deep learning accelerators based on readily available device technologies.

0 citations0 reviewsNo code linkedOpen access
preprint2016arXiv

A monolithic 56 Gb/s silicon photonic pulse-amplitude modulation transmitter

Silicon photonics promises to address the challenges for next-generation short-reach optical interconnects. Growing bandwidth demand in hyper-scale data centers and high-performance computing motivates the development of faster and more-efficient silicon photonics links. While it is challenging to raise the serial line rate, further scaling of the data rate can be realized by, for example, increasing the number of parallel fibers, increasing the number of wavelengths per fiber, and using multi-level pulse-amplitude modulation (PAM). Among these approaches, PAM has a unique advantage because it does not require extra lasers or a costly overhaul of optical fiber cablings within the existing infrastructure. Here, we demonstrate the first fully monolithically integrated silicon photonic four-level PAM (PAM-4) transmitter operating at 56 Gb/s and demonstrate error-free transmission (bit-error-rate < 10$^{-12}$) up to 50 Gb/s without forward error correction. The superior PAM-4 waveform is enabled by optimization of silicon traveling wave modulators and monolithic integration of the CMOS driver circuits. Our results show that monolithic silicon photonics technology is a promising platform for future ultrahigh data rate optical interconnects.

0 citations0 reviewsNo code linkedOpen access
preprint2015arXiv

A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime - Part II Extrinsic Elements, Performance Assessment, and Design Optimization

We present a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) including contact resistance, direct source-to-drain and band-to-band tunneling currents. The model captures the effects of dimensional scaling and performance degradations due to parasitic effects and is used to study the trade-offs between the drive current and leakage current of CNFETs according to the selection of CNT diameter, CNT density, contact length, and gate length for a target contacted gate pitch. We describe a co-optimization study of CNFET device parameters near the limits of scaling with physical insight, and project the CNFET performance at the 5-nm technology node with an estimated contacted gate pitch of 31 nm. Based on the analysis including parasitic resistance, capacitance, and tunneling leakage current, a CNT density of 180 CNTs/μm will enable CNFET technology to meet the ITRS target of drive current (1.33 mA/μm), which is within reach of modern experimental capabilities

0 citations0 reviewsNo code linkedOpen access
preprint2015arXiv

A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime-Part I Intrinsic Elements

We presents a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) based on the virtual-source (VS) approach, describing the intrinsic current-voltage and charge-voltage characteristics. The features of the model include: (i) carrier VS velocity extracted from experimental devices with gate lengths down to 15 nm; (ii) carrier effective mobility and velocity depending on the CNT diameter; (iii) short channel effect such as inverse subthreshold slope degradation and drain-induced barrier lowering depending on the device dimensions; (iv) small-signal capacitances including the CNT quantum capacitance effect to account for the decreasing gate capacitance at high gate bias. The CNFET model captures dimensional scaling effects and is suitable for technology benchmarking and performance projection at the sub-10-nm technology nodes.

0 citations0 reviewsNo code linkedOpen access
preprint2013arXiv

Comparative Study of Chemically Synthesized and Exfoliated Multilayer MoS2 Field-Effect Transistors

We report the realization of field-effect transistors (FETs) made with chemically synthesized multilayer 2D crystal semiconductor MoS2. Electrical properties such as the FET mobility, subthreshold swing, on/off ratio, and contact resistance of chemically synthesized (s-) MoS2 are indistinguishable from that of mechanically exfoliated (x-) MoS2, however flat-band voltages are different, possibly due to polar chemical residues originating in the transfer process. Electron diffraction studies and Raman spectroscopy show the structural similarity of s-MoS2 to x-MoS2. This initial report on the behavior and properties of s-MoS2 illustrates the feasibility of electronic devices using synthetic layered 2D crystal semiconductors.

0 citations0 reviewsNo code linkedOpen access
preprint2013arXiv

Graphene Nanoribbon Field-Effect Transistors on Wafer-Scale Epitaxial Graphene on SiC substrates

We report the realization of top-gated graphene nanoribbon field effect transistors (GNRFETs) of ~10 nm width on large-area epitaxial graphene exhibiting the opening of a band gap of ~0.14 eV. Contrary to prior observations of disordered transport and severe edge-roughness effects of GNRs, the experimental results presented here clearly show that the transport mechanism in carefully fabricated GNRFETs is conventional band-transport at room temperature, and inter-band tunneling at low temperature. The entire space of temperature, size, and geometry dependent transport properties and electrostatics of the GNRFETs are explained by a conventional thermionic emission and tunneling current model. Our combined experimental and modeling work proves that carefully fabricated narrow GNRs behave as conventional semiconductors, and remain potential candidates for electronic switching devices.

0 citations0 reviewsNo code linkedOpen access
preprint2013arXiv

High-Voltage Field Effect Transistors with Wide-Bandgap β-Ga2O3 Nanomembranes

Nanoscale semiconductor materials have been extensively investigated as the channel materials of transistors for energy-efficient low-power logic switches to enable scaling to smaller dimensions. On the opposite end of transistor applications is power electronics for which transistors capable of switching very high voltages are necessary. Miniaturization of energy-efficient power switches can enable the integration with various electronic systems and lead to substantial boosts in energy efficiency. Nanotechnology is yet to have an impact in this arena. In this work, it is demonstrated that nanomembranes of the wide-bandgap semiconductor gallium oxide can be used as channels of transistors capable of switching high voltages, and at the same time can be integrated on any platform. The findings mark a step towards using lessons learnt in nanomaterials and nanotechnology to address a challenge that yet remains untouched by the field.

0 citations0 reviewsNo code linkedOpen access
preprint2013arXiv

Schottky-to-Ohmic Crossover in Carbon Nanotube Transistor Contacts

For carbon nanotube transistors, as for graphene, the electrical contacts are a key factor limiting device performance. We calculate the device characteristics as a function of nanotube diameter and metal workfunction. Although the on-state current varies continuously, the transfer characteristics reveal a relatively abrupt crossover from Schottky to ohmic contacts. We find that typical high-performance devices fall surprisingly close to the crossover. Surprisingly, tunneling plays an important role even in this regime, so that current fails to saturate with gate voltage as was expected due to "source exhaustion".

0 citations0 reviewsNo code linkedOpen access
preprint2010arXiv

On the possibility of obtaining MOSFET-like performance and sub-60 mV/decade swing in 1D broken-gap tunnel transistors

Tunneling field-effect transistors (TFETs) have gained a great deal of recent interest due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been achieving high drive currents, which is a prerequisite for high-performance operation. In this paper we explore the performance potential of a 1D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, and the carbon nanotube bandstructure as the model 1D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation, and show that it can indeed produce less than 60mV/decade subthreshold swing at room temperature even in the presence of electron-phonon scattering. The 1D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications.

0 citations0 reviewsNo code linkedOpen access