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Emerging Technologies

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preprint2016arXiv

Nonvolatile Multi-level Memory and Boolean Logic Gates Based on a Single Memtranstor

Memtranstor that correlates charge and magnetic flux via nonlinear magnetoelectric effects has a great potential in developing next-generation nonvolatile devices. In addition to multi-level nonvolatile memory, we demonstrate here that nonvolatile logic gates such as NOR and NAND can be implemented in a single memtranstor made of the Ni/PMN-PT/Ni heterostructure. After applying two sequent voltage pulses (X1, X2) as the logic inputs on the memtranstor, the output magnetoelectric voltage can be positive high (logic "1"), positive low (logic "0"), or negative (logic "0"), depending on the levels of X1 and X2. The underlying physical mechanism is related to the complete or partial reversal of ferroelectric polarization controlled by inputting selective voltage pulses, which determines the magnitude and sign of the magnetoelectric voltage coefficient. The combined functions of both memory and logic could enable the memtranstor as a promising candidate for future computing systems beyond von Neumann architecture.

preprint2016arXiv

Complete DFM Model for High-Performance Computing SoCs with Guard Ring and Dummy Fill Effect

For nanotechnology, the semiconductor device is scaled down dramatically with additional strain engineering for device enhancement, the overall device characteristic is no longer dominated by the device size but also circuit layout. The higher order layout effects, such as well proximity effect (WPE), oxide spacing effect (OSE) and poly spacing effect (PSE), play an important role for the device performance, it is critical to understand Design for Manufacturability (DFM) impacts with various layout topology toward the overall circuit performance. Currently, the layout effects (WPE, OSE and PSE) are validated through digital standard cell and analog differential pair test structure. However, two analog layout structures: the guard ring and dummy fill impact are not well studied yet, then, this paper describes the current mirror test circuit to examine the guard ring and dummy fills DFM impacts using TSMC 28nm HPM process.

preprint2016arXiv

An Overview of Mobile Capacitive Touch Technologies Trends

Touch sensing, as a major human/machine interface, is widely used in various commercial products such as smart watches, mobile phones, tablets and TVs. State-of-the-art touch detections are mainly based on mutual capacitive sensing, which requires necessary contact-touch, limiting the mobile user experience. Recently, remote gesture sensing is widely reported in both academy and industry as it can provide additional user-experience for mobile interface. The capacitive remote gesture sensing is mainly based on detecting self-capacitance, achieving high resolution through eliminating the parasitic mutual capacitance. In this work, we overview the different generations of touchscreen technology, comparing the touch and remote gesture sensing technologies difference. In addition, different remote gesture sensing technologies are also compared. The limitations and potentials of different topologies are discussed and a final conclusion about the technology trends is summarized in the end.

preprint2016arXiv

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

This paper investigates the potentials of using a hybrid memristor CMOS technology, called MeMOS, for the realisation of ternary adders. Ternary adders exploit the qualitative advantage of multi-value storage capability of memristors compared to conventional CMOS flip-flops storing only binary values in one cell. Furthermore they carry out an addition in $O(1)$ and are therefore considered. The MeMOS approach is compared to a CMOS solution for the ternary adders using multi value memristors as registers concerning the achievable latency and the energy consumption. It is shown that using the TEAM, VTEAM model and a model considering commercially available memristors from Known the approach of using CMOS ternary adders using memristors as multi-value register memory is to prefer. MeMOS circuits have advantages for a static operation mode, i.e. if they are operated after a reset.

preprint2017arXiv

High Performance CNFET-based Ternary Full Adders

This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET technology. The proposed methods are simulated at different conditions such as different supply voltages, different temperature and operational frequencies. Simulation results show that the proposed designs are faster than the state of the art CNFET based ternary full adders.

preprint2016arXiv

Posner computing: a quantum neural network model

We present a construction, rendered in Quipper, of a quantum algorithm which probabilistically computes a classical function from n bits to n bits. The construction is intended to be of interest primarily for the features of Quipper it highlights. However, intrigued by the utility of quantum information processing in the context of neural networks, we present the algorithm as a simplest example of a particular quantum neural network which we first define. As the definition is inspired by recent work of Fisher concerning possible quantum substrates to cognition, we precede it with a short description of that work.

preprint2017arXiv

Radio Frequency Modulated Signaling Interconnect for Memory-to-Processor and Processor-to-Processor Interfaces: An Overview

With the evolution of heterogeneous computing system, such as network-on-chip, high-performance distributed computing, accelerator-rich architectures and cluster computing, high-speed, energy-efficient and low-latency interfaces among memory-to-processor and processor-to-processor become the key technology to enable those technologies. Simultaneously, the scaling of CMOS makes the switching speed of the transistor up to sub-THz. Radio-frequency or even millimeter-wave modulated signaling interconnect has unique features in ultra-low power operation, dynamic allocation of bandwidth and low latency, compared with convention baseband signaling interconnect. In this work, we overview the different generations of radio-frequency interconnect (RF-I) technology, compare them with conventional baseband signaling interconnect technologies. The limitations and potentials are also discussed in the end.

preprint2016arXiv

Parallel photonic reservoir computing using frequency multiplexing of neurons

Today's unrelenting increase in demand for information processing creates the need for novel computing concepts. Reservoir computing is such a concept that lends itself particularly well to photonic hardware implementations. Over recent years, these hardware implementations have gained maturity and now achieve state-of-the-art performance on several benchmark tasks. However, implementations so far are essentially all based on sequential data processing, leaving the inherent parallelism of photonics unexploited. Parallel implementations process all neurons simultaneously, and therefore have the potential of reducing computation time by a factor equal to the number of neurons, compared to sequential architectures. Here, we report a parallel reservoir computer that uses frequency domain multiplexing of neuron states. We illustrate its performance on standard benchmark tasks such as nonlinear channel equalization, the reproduction of a nonlinear 10th-order system, and speech recognition, obtaining error rates similar to previous optical experiments. The present experiment is thus an important step towards high speed, low footprint, all optical photonic information processing.

preprint2016arXiv

Hierarchical Self-Assembly of Fractals with Signal-Passing Tiles

In this paper, we present high-level overviews of tile-based self-assembling systems capable of producing complex, infinite, aperiodic structures known as discrete self-similar fractals. Fractals have a variety of interesting mathematical and structural properties, and by utilizing the bottom-up growth paradigm of self-assembly to create them we not only learn important techniques for building such complex structures, we also gain insight into how similar structural complexity arises in natural self-assembling systems. Our results fundamentally leverage hierarchical assembly processes, and use as our building blocks square "tile" components which are capable of activating and deactivating their binding "glues" a constant number of times each, based only on local interactions. We provide the first constructions capable of building arbitrary discrete self-similar fractals at scale factor 1, and many at temperature 1 (i.e. "non-cooperatively"), including the Sierpinski triangle.

preprint2016arXiv

A modified Physarum-inspired model for the user equilibrium traffic assignment problem

The user equilibrium traffic assignment principle is very important in the traffic assignment problem. Mathematical programming models are designed to solve the user equilibrium problem in traditional algorithms. Recently, the Physarum shows the ability to address the user equilibrium and system optimization traffic assignment problems. However, the Physarum model are not efficient in real traffic networks with two-way traffic characteristics and multiple origin-destination pairs. In this article, a modified Physarum-inspired model for the user equilibrium problem is proposed. By decomposing traffic flux based on origin nodes, the traffic flux from different origin-destination pairs can be distinguished in the proposed model. The Physarum can obtain the equilibrium traffic flux when no shorter path can be discovered between each origin-destination pair. Finally, numerical examples use the Sioux Falls network to demonstrate the rationality and convergence properties of the proposed model.

preprint2016arXiv

Enabling Bio-Plausible Multi-level STDP using CMOS Neurons with Dendrites and Bistable RRAMs

Large-scale integration of emerging nanoscale non-volatile memory devices, e.g. resistive random-access memory (RRAM), can enable a new generation of neuromorphic computers that can solve a wide range of machine learning problems. Such hybrid CMOS-RRAM neuromorphic architectures will result in several orders of magnitude reduction in energy consumption at a very small form factor, and herald autonomous learning machines capable of self-adapting to their environment. However, the progress in this area has been impeded from the realization that the actual memory devices fall well short of their expected behavior. In this work, we discuss the challenges associated with these memory devices and their use in neuromorphic computing circuits, and propose pathways to overcome these limitations by introducing 'dendritic learning'.

preprint2016arXiv

Type Based Sign Modulation and its Application for ISI mitigation in Molecular Communication

An important challenge in design of modulation schemes for molecular communication is positivity of the transmission signal (only a positive concentration of molecules can be released in the environment). This restriction makes handling of the InterSymbol Interference (ISI) a challenge for molecular communication. Previous works have proposed use of chemical reactions to remove molecules from the environment, and to effectively simulate negative signals. However, the differential equation describing a diffusion-reaction process is non-linear. This precludes the possibility of using Fourier transform tools. In this paper, a solution for simulating negative signals based on the diffusion-reaction channel model is proposed. While the proposed solution does not exploit the full degrees of freedom available for signaling in a diffusion-reaction process, but its end-to-end system is a linear channel and amenable to Fourier transform analysis. Based on our solution, a modulation scheme and a precoder are introduced and shown to have a significant reduction in error probability compared to previous modulation schemes such as CSK and MCSK. The effect of various imperfections (such as quanti

preprint2016arXiv

An Energy-Efficient VCO-Based Matrix Multiplier Block to Support On-Chip Image Analysis

Images typically are represented as uniformly sampled data in the form of matrix of pixels/voxels. Therefore, matrix multiply-and-accumulate (MAC) forms the core of most state-of-the-art image analysis algorithms. While digital implementation of MAC has generally been the preferred approach, high power consumption is an impediment to adopting it for medical image analysis. In this work, we present a time-domain signal processing architecture which performs MAC operations with 7bit accuracy while consuming 400X lower energy than digital implementation. The proposed architecture performs analog computation using mostly digital circuits and is suitable for scaled CMOS technologies. The proposed time-domain MAC architecture is expected to play a central role in empowering the advancement of various on-chip image analysis operations.

preprint2016arXiv

Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems

Over the past decade Spiking Neural Networks (SNN) have emerged as one of the popular architectures to emulate the brain. In SNN, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing dependent plasticity mechanisms require the online programming of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike transmission and programming current paths. The spintronic synapse consists of a ferromagnet-heavy metal heterostructure where programming current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programming energy and fast programming times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in transistor sub-threshold region to form a network of spiking neurons that can be utilized for pattern recognition problems.

preprint2016arXiv

Memristor Threshold Logic: An Overview to Challenges and Applications

Once referred to as the missing circuit component, memristor has come long way across to be recognized and taken as important to future circuit designs. The memristor due to its ability to memorize the state, switch between different resistance level, smaller size and low leakage currents makes it useful for a wide range of intelligent memory and computing applications. This overview paper highlights broadly provides the uses of memristor in the implementation of cognitive cells for different imaging and pattern matching applications.

preprint2016arXiv

Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing

A switched-capacitor matrix multiplier is presented for approximate computing and machine learning applications. The multiply-and-accumulate operations perform discrete-time charge-domain signal processing using passive switches and 300 aF unit capacitors. The computation is digitized with a 6 b asynchronous successive approximation register analog-to-digital converter. The analyses of incomplete charge accumulation and thermal noise are discussed. The design was fabricated in 40 nm CMOS, and experimental measurements of multiplication are illustrated using matched filtering and image convolutions to analyze noise and offset. Two applications are highlighted: 1) energy-efficient feature extraction layer performing both compression and classification in a neural network for an analog front end and 2) analog acceleration for solving optimization problems that are traditionally performed in the digital domain. The chip obtains measured efficiencies of 8.7 TOPS/W at 1 GHz for the first application and 7.7 TOPS/W at 2.5 GHz for the second application.

preprint2016arXiv

Design Automation and Design Space Exploration for Quantum Computers

A major hurdle to the deployment of quantum linear systems algorithms and recent quantum simulation algorithms lies in the difficulty to find inexpensive reversible circuits for arithmetic using existing hand coded methods. Motivated by recent advances in reversible logic synthesis, we synthesize arithmetic circuits using classical design automation flows and tools. The combination of classical and reversible logic synthesis enables the automatic design of large components in reversible logic starting from well-known hardware description languages such as Verilog. As a prototype example for our approach we automatically generate high quality networks for the reciprocal $1/x$, which is necessary for quantum linear systems algorithms.

preprint2016arXiv

High-Bandwidth and Large Coupling Tolerance Graded-Index Multimode Polymer Waveguides for On-board High-Speed Optical Interconnects

Optical interconnects have attracted significant research interest for use in short-reach board-level optical communication links in supercomputers and data centres. Multimode polymer waveguides in particular constitute an attractive technology for on-board optical interconnects as they provide high bandwidth, offer relaxed alignment tolerances, and can be cost-effectively integrated onto standard printed circuit boards (PCBs). However, the continuing improvements in bandwidth performance of optical sources make it important to investigate approaches to develop high bandwidth polymer waveguides. In this paper, we present dispersion studies on a graded-index (GI) waveguide in siloxane materials designed to deliver high bandwidth over a range of launch conditions. Bandwidth-length products of >70 GHzxm and ~65 GHzxm are observed using a 50/125 um multimode fibre (MMF) launch for input offsets of +/- 10 um without and with the use of a mode mixer respectively; and enhanced values of >100 GHzxm are found under a 10x microscope objective launch for input offsets of ~18 x 20 um^2. The large range of offsets is within the -1 dB alignment tolerances. A theoretical model is developed using

preprint2016arXiv

Sub 100nW volatile nano-metal-oxide memristor as synaptic-like encoder of neuronal spikes

Advanced neural interfaces mediate a bio-electronic link between the nervous system and microelectronic devices, bearing great potential as innovative therapy for various diseases. Spikes from a large number of neurons are recorded leading to creation of big data that require on-line processing under most stringent conditions, such as minimal power dissipation and on-chip space occupancy. Here, we present a new concept where the inherent volatile properties of a nano-scale memristive device are used to detect and compress information on neural spikes as recorded by a multi-electrode array. Simultaneously, and similarly to a biological synapse, information on spike amplitude and frequency is transduced in metastable resistive state transitions of the device, which is inherently capable of self-resetting and of continuous encoding of spiking activity. Furthermore, operating the memristor in a very high resistive state range reduces its average in-operando power dissipation to less than 100 nW, demonstrating the potential to build highly scalable, yet energy-efficient on-node processors for advanced neural interfaces.

preprint2016arXiv

Two-Dimensional Oscillatory Neural Network Based on Charge-Density-Wave Devices Operating at Room Temperature

We propose an oscillatory neural network implemented with two-dimensional tantalum disulfide devices operating in the change density wave regime at room temperature. An elementary cell of the network consists of two 1T-TaS2 devices connected in series. Such a cell has constant output and oscillatory states. All cells have the same bias voltage. There is constant current flowing through the cell in the constant output mode. The oscillations occur at a certain bias voltage due to the electrical-field driven metal-to-insulator transition owing to the changes in the charge density wave phase in the 1T-TaS2 channel. Two 1T-TaS2 devices oscillate out-of-phase where one of the devices is in the insulator phase while the other one is in the metallic state. The nearest-neighbor cells are coupled via graphene transistors. The cells are resistively coupled if the graphene transistor is in the On state while they are capacitively coupled if the transistor is in the Off state. The operation of the oscillatory neural network is simulated numerically for the 30x30 node network. The results of our numerical modeling show the formation of artificial vortexes and cellular-automata type data processi

preprint2016arXiv

Highly-Secure Physically Unclonable Cryptographic Primitives Using Nonlinear Conductance and Analog State Tuning in Memristive Crossbar Arrays

The rapidly expanding hardware-intrinsic security primitives are aimed at addressing significant security challenges of a massively interconnected world in the age of information technology. The main idea of such primitives is to employ instance-specific process-induced variations in electronic hardware as a source of cryptographic data. Among the emergent technologies, memristive devices provide unique opportunities for security applications due to the underlying stochasticity in their operation. Herein, we report a prototype of a robust, dense, and reconfigurable physical unclonable function primitives based on the three-dimensional passive metal-oxide memristive crossbar circuits, by making positive use of process-induced variations in the devices' nonlinear I-Vs and their analog tuning. We first characterize security metrics for a basic building block of the security primitives based on a two layer stack with monolithically integrated 10x10 250-nm half-pitch memristive crossbar circuits. The experimental results show that the average uniformity and diffusivity, measured on a random sample of 6,000 64-bit responses, out of ~697,000 total, is close to ideal 50% with 5% standa

preprint2016arXiv

MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic

In the quest for novel, scalable and energy-efficient computing technologies, many non-charge based logic devices are being explored. Recent advances in multi-ferroic materials have paved the way for electric field induced low energy and fast switching of nano-magnets using the magneto-electric (ME) effect. In this paper, we propose a voltage driven logic-device based on the ME induced switching of nano-magnets. We further demonstrate that the proposed logic-device, which exhibits decoupled read and write paths, can be used to construct a complete logic family including XNOR, NAND and NOR gates. The proposed logic family shows good scalability with a quadratic dependence of switching energy with respect to the switching voltage. Further, the proposed logic-device has better robustness against the effect of thermal noise as compared to the conventional current driven switching of nano-magnets. A device-to-circuit level coupled simulation framework, including magnetization dynamics and electron transport model, has been developed for analyzing the present proposal. Using our simulation framework, we present energy and delay results for the proposed Magneto-Electric Spin Logic (MESL)

preprint2016arXiv

A Machine Learning Approach to Model the Received Signal in Molecular Communications

A molecular communication channel is determined by the received signal. Received signal models form the basis for studies focused on modulation, receiver design, capacity, and coding depend on the received signal models. Therefore, it is crucial to model the number of received molecules until time $t$ analytically. Modeling the diffusion-based molecular communication channel with the first-hitting process is an open issue for a spherical transmitter. In this paper, we utilize the artificial neural networks technique to model the received signal for a spherical transmitter and a perfectly absorbing receiver (i.e., first hitting process). The proposed technique may be utilized in other studies that assume a spherical transmitter instead of a point transmitter.

preprint2014arXiv

Performance of Macro-Scale Molecular Communications with Sensor Cleanse Time

In this paper, we consider a molecular diffusion based communications link that conveys information on the macro-scale (several metres). The motivation is to apply molecular-based communications to challenging electromagnetic environments. We first derive a novel capture probability expression of a finite sized receiver. The paper then introduces the concept of time-aggregated molecular noise at the receiver as a function of the rate at which the sensor can self-cleanse. The resulting inter-symbol-interference is expressed as a function of the sensor cleanse time, and the performance metrics of bit error rate, throughput and round-trip-time are derived. The results show that the performance is very sensitive to the sensor cleanse time and the drift velocity. The paper concludes with recommendations on the design of a real communication link based on these findings and applies the concepts to a test-bed.

535 works