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Researcher profile

Amlan Chakrabarti

Amlan Chakrabarti contributes to research discovery and scholarly infrastructure.

ResearcherAffiliation not importedOpen to collaborate
quant-phArtificial IntelligenceEmerging TechnologiesHardware ArchitectureComputation and LanguageCryptography and SecurityData Structures and AlgorithmsMachine Learning

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Published work

13 published item(s)

preprint2026arXiv

A New Technique for AI Explainability using Feature Association Map

Lack of transparency in AI systems poses challenges in critical real-life applications. It is important to be able to explain the decisions of an AI system to ensure trust on the system. Explainable AI (XAI) algorithms play a vital role in achieving this objective. In this paper, we are proposing a new algorithm for Explaining AI systems, FAMeX (Feature Association Map based eXplainability). The proposed algorithm is based on a graph-theoretic formulation of the feature set termed as Feature Association Map (FAM). The foundation of the modelling is based on association between features. The proposed FAMeX algorithm has been found to be better than the competing XAI algorithms - Permutation Feature Importance (PFI) and SHapley Additive exPlanations (SHAP). Experiments conducted with eight benchmark algorithms show that FAMeX is able to gauge feature importance in the context of classification better than the competing algorithms. This definitely shows that FAMeX is a promising algorithm in explaining the predictions from an AI system

0 citations0 reviewsNo code linkedOpen access
preprint2026arXiv

PHISHREV: A Hybrid Machine Learning and Post-Hoc Non-monotonic Reasoning Framework for Context-Aware Phishing Website Classification

Phishing detection systems are predominantly rely on statistical machine learning models, which often lack contextual reasoning and are vulnerable to adversarial manipulation. In this work, we propose a hybrid framework that integrates machine learning classifiers with non-monotonic reasoning using Answer Set Programming (ASP) to enable context-aware decision refinement. The proposed post-hoc reasoning layer incorporates expert knowledge to revise classifier predictions through formal belief revisions. Experimental results indicate that the reasoning module modifies 5.08\% of classifier outputs, leading to improved decision consistency. A key advantage is that new domain knowledge can be incorporated into the reasoning layer in $\mathcal{O}(n)$ time, eliminating the need for model retraining.

0 citations0 reviewsNo code linkedOpen access
preprint2025arXiv

From Transformers to LLMs: A Systematic Survey of Efficiency Considerations in NLP

The emergence of Transformer-based Large Language Models (LLMs) has substantially augmented the capabilities of Natural Language Processing (NLP), thereby intensifying the demand for computational resources. Therefore, enhancing efficiency based on factors like computational requirements, energy consumption, carbon footprint and financial cost has become a vital area of research. This motivates us to conduct a systematic literature review on Transformer-based LLMs in NLP from the perspective of efficiency. In this survey of 312 articles published between the years 2011 and 2025, efficiency-improvement endeavors have been systematically discussed targeting various aspects such as data curation, model design, model downsizing, and dynamic inferencing. This has been augmented with efficiency considerations in model adaptation strategies like pre-training, fine-tuning, prompt-engineering and Retrieval-Augmented Generation (RAG). Furthermore, a statistical analysis of the articles has been performed followed by an in-depth evaluation of the efficiency and efficacy of more than 30 renowned NLP models has been conducted on 13 evaluation benchmarks. This paper offers valuable insights for researchers, professionals as well as scholars, and explores the trend of research toward sustainable practices in NLP.

0 citations0 reviewsNo code linkedOpen access
preprint2022arXiv

Asymptotically Improved Circuit for $d$-ary Grover's Algorithm with Advanced Decomposition of $n$-qudit Toffoli Gate

The progress in building quantum computers to execute quantum algorithms has recently been remarkable. Grover's search algorithm in a binary quantum system provides considerable speed-up over classical paradigm. Further, Grover's algorithm can be extended to a $d$-ary (qudit) quantum system for utilizing the advantage of larger state space, which helps to reduce the run-time of the algorithm as compared to the traditional binary quantum systems. In a qudit quantum system, an $n$-qudit Toffoli gate plays a significant role in the accurate implementation of Grover's algorithm. In this article, a generalized $n$-qudit Toffoli gate has been realized using higher dimensional qudits to attain a logarithmic depth decomposition without ancilla qudit. The circuit for Grover's algorithm has then been designed for any $d$-ary quantum system, where $d \ge 2$, with the proposed $n$-qudit Toffoli gate to obtain optimized depth compared to earlier approaches. The technique for decomposing an $n$-qudit Toffoli gate requires access to two immediately higher energy levels, making the design susceptible to errors. Nevertheless, we show that the percentage decrease in the probability of error is significant as we have reduced both gate count and circuit depth as compared to that in state-of-the-art works.

0 citations0 reviewsNo code linkedOpen access
preprint2022arXiv

Intermediate Qutrit-based Improved Quantum Arithmetic Operations with Application on Financial Derivative Pricing

In some quantum algorithms, arithmetic operations are of utmost importance for resource estimation. In binary quantum systems, some efficient implementation of arithmetic operations like, addition/subtraction, multiplication/division, square root, exponential and arcsine etc. have been realized, where resources are reported as a number of Toffoli gates or T gates with ancilla. Recently it has been demonstrated that intermediate qutrits can be used in place of ancilla, allowing us to operate efficiently in the ancilla-free frontier zone. In this article, we have incorporated intermediate qutrit approach to realize efficient implementation of all the quantum arithmetic operations mentioned above with respect to gate count and circuit-depth without T gate and ancilla. Our resource estimates with intermediate qutrits could guide future research aimed at lowering costs considering arithmetic operations for computational problems. As an application of computational problems, related to finance, are poised to reap the benefit of quantum computers, in which quantum arithmetic circuits are going to play an important role. In particular, quantum arithmetic circuits of arcsine and square root are necessary for path loading using the re-parameterization method, as well as the payoff calculation for derivative pricing. Hence, the improvements are studied in the context of the core arithmetic circuits as well as the complete application of derivative pricing. Since our intermediate qutrit approach requires to access higher energy levels, making the design prone to errors, nevertheless, we show that the percentage decrease in the probability of error is significant owing to the fact that we achieve circuit robustness compared to qubit-only works.

0 citations0 reviewsNo code linkedOpen access
preprint2022arXiv

Towards Power Efficient DNN Accelerator Design on Reconfigurable Platform

The exponential emergence of Field Programmable Gate Array (FPGA) has accelerated the research of hardware implementation of Deep Neural Network (DNN). Among all DNN processors, domain specific architectures, such as, Google's Tensor Processor Unit (TPU) have outperformed conventional GPUs. However, implementation of TPUs in reconfigurable hardware should emphasize energy savings to serve the green computing requirement. Voltage scaling, a popular approach towards energy savings, can be a bit critical in FPGA as it may cause timing failure if not done in an appropriate way. In this work, we present an ultra low power FPGA implementation of a TPU for edge applications. We divide the systolic-array of a TPU into different FPGA partitions, where each partition uses different near threshold (NTC) biasing voltages to run its FPGA cores. The biasing voltage for each partition is roughly calculated by the proposed static schemes. However, further calibration of biasing voltage is done by the proposed runtime scheme. Four clustering algorithms based on the minimum slack value of different design paths of Multiply Accumulates (MACs) study the partitioning of FPGA. To overcome the timing failure caused by NTC, the MACs which have higher minimum slack are placed in lower voltage partitions and the MACs have lower minimum slack path are placed in higher voltage partitions. The proposed architecture is simulated in a commercial platform : Vivado with Xilinx Artix-7 FPGA and academic platform VTR with 22nm, 45nm, 130nm FPGAs. The simulation results substantiate the implementation of voltage scaled TPU in FPGAs and also justifies its power efficiency.

0 citations0 reviewsNo code linkedOpen access
preprint2021arXiv

Circuit Design for $k$-coloring Problem and Its Implementation in Any Dimensional Quantum System

With the evolution of quantum computing, researchers now-a-days tend to incline to find solutions to NP-complete problems by using quantum algorithms in order to gain asymptotic advantage. In this paper, we solve $k$-coloring problem (NP-complete problem) using Grover's algorithm in any dimensional quantum system or any $d$-ary quantum system for the first time to the best of our knowledge, where $d \ge 2$. A newly proposed comparator-based approach helps to generalize the implementation of the $k$-coloring problem in any dimensional quantum system. Till date, $k$-coloring problem has been implemented only in binary and ternary quantum system, hence, we abide to $d=2$ or $d=3$, that is for binary and ternary quantum system for comparing our proposed work with the state-of-the-art techniques. This proposed approach makes the reduction of the qubit cost possible, compared to the state-of-the-art binary quantum systems. Further, with the help of newly proposed ternary comparator, a substantial reduction in quantum gate count for the ternary oracle circuit of the $k$-coloring problem than the previous approaches has been obtained. An end-to-end automated framework has been put forward for implementing the $k$-coloring problem for any undirected and unweighted graph on any available Near-term quantum devices or Noisy Intermediate-Scale Quantum (NISQ) devices or multi-valued quantum simulator, which helps in generalizing our approach.

0 citations0 reviewsNo code linkedOpen access
preprint2021arXiv

Circuit Design for Clique Problem and Its Implementation on Quantum Computer

Finding cliques in a graph has several applications for its pattern matching ability. $k$-clique problem, a special case of clique problem, determines whether an arbitrary graph contains a clique of size $k$, has already been addressed in quantum domain. A variant of $k$-clique problem that lists all cliques of size $k$, has also popular modern-day applications. Albeit, the implementation of such variant of $k$-clique problem in quantum setting still remains untouched. In this paper, apart from theoretical solution of such $k$-clique problem, practical quantum gate-based implementation has been addressed using Grover's algorithm. This approach is further extended to design circuit for the maximum clique problem in classical-quantum hybrid architecture. The algorithm automatically generates the circuit for any given undirected and unweighted graph and any given $k$, which makes our approach generalized in nature. The proposed approach of solving $k$-clique problem has exhibited a reduction of qubit cost and circuit depth as compared to the state-of-the-art approach, for a small $k$ with respect to a large graph. A framework that can map the automated generated circuit for clique problem to quantum devices is also proposed. An analysis of the experimental results is demonstrated using IBM's Qiskit.

0 citations0 reviewsNo code linkedOpen access
preprint2021arXiv

Faster Search of Clustered Marked States with Lackadaisical Quantum Walks

The nature of discrete-time quantum walk in the presence of multiple marked states has been studied by Nahimovs and Rivosh. They introduced an exceptional configuration of clustered marked states $i.e.,$ if the marked states are arranged in a $\sqrt{k} \times \sqrt{k}$ cluster within a $\sqrt{N} \times \sqrt{N}$ grid, where $k=n^{2}$ and $n$ an odd integer. They showed that finding a single marked state among the multiple ones using quantum walk with AKR (Ambainis, Kempe and Rivosh) coin requires $Ω(\sqrt{N} - \sqrt{k})$ time. Furthermore, Nahimov and Rivosh also showed that the Grover's coin can find the same configuration of marked state both faster and with higher probability compared to that with the AKR coin. In this article, we show that using lackadaisical quantum walk, a variant of a three-state discrete-time quantum walk on a line, the success probability of finding all the clustered marked states of this exceptional configuration is nearly 1 with smaller run-time. We also show that the weights of the self-loop suggested for multiple marked states in the state-of-the-art works are not optimal for this exceptional configuration of clustered mark states. We propose a range of weights of the self-loop from which only one can give the desired result for this configuration.

0 citations0 reviewsNo code linkedOpen access
preprint2021arXiv

Moving Quantum States without SWAP via Intermediate Higher Dimensional Qudits

Quantum algorithms can be realized in the form of a quantum circuit. To map quantum circuit for specific quantum algorithm to quantum hardware, qubit mapping is an imperative technique based on the qubit topology. Due to the neighbourhood constraint of qubit topology, the implementation of quantum algorithm rightly, is essential for moving information around in a quantum computer. Swapping of qubits using SWAP gate moves the quantum state between two qubits and solves the neighbourhood constraint of qubit topology. Though, one needs to decompose the SWAP gate into three CNOT gates to implement SWAP gate efficiently, but unwillingly quantum cost with respect to gate count and depth increases. In this paper, a new formalism of moving quantum states without using SWAP operation is introduced for the first time to the best of our knowledge. Moving quantum states through qubits have been attained with the adoption of temporary intermediate qudit states. This introduction of intermediate qudit states has exhibited a three times reduction in quantum cost with respect to gate count and approximately two times reduction in respect to circuit depth compared to the state-of-the-art approach of SWAP gate insertion. Further, the proposed approach is generalized to any dimensional quantum system.

0 citations0 reviewsNo code linkedOpen access
preprint2021arXiv

Qurzon: A Prototype for a Divide and Conquer Based Quantum Compiler

When working with algorithms on quantum devices, quantum memory becomes a crucial bottleneck due to low qubit count in NISQ-era devices. In this context, the concept of `divide and compute', wherein a quantum circuit is broken into several subcircuits and executed separately, while stitching the results of the circuits via classical post-processing, becomes a viable option, especially in NISQ-era devices. This paper introduces \textbf{Qurzon}, a proposed novel quantum compiler that incorporates the marriage of techniques of divide and compute with the state-of-the-art algorithms of optimal qubit placement for executing on real quantum devices. A scheduling algorithm is also introduced within the compiler that can explore the power of distributed quantum computing while paving the way for quantum parallelism for large algorithms. Several benchmark circuits have been executed using the compiler, thereby demonstrating the power of the divide and compute when working with real NISQ-era quantum devices.

0 citations0 reviewsNo code linkedOpen access
preprint2020arXiv

2D Qubit Placement of Quantum Circuits using LONGPATH

In order to achieve speedup over conventional classical computing for finding solution of computationally hard problems, quantum computing was introduced. Quantum algorithms can be simulated in a pseudo quantum environment, but implementation involves realization of quantum circuits through physical synthesis of quantum gates. This requires decomposition of complex quantum gates into a cascade of simple one qubit and two qubit gates. The methodological framework for physical synthesis imposes a constraint regarding placement of operands (qubits) and operators. If physical qubits can be placed on a grid, where each node of the grid represents a qubit then quantum gates can only be operated on adjacent qubits, otherwise SWAP gates must be inserted to convert non-Linear Nearest Neighbor architecture to Linear Nearest Neighbor architecture. Insertion of SWAP gates should be made optimal to reduce cumulative cost of physical implementation. A schedule layout generation is required for placement and routing apriori to actual implementation. In this paper, two algorithms are proposed to optimize the number of SWAP gates in any arbitrary quantum circuit. The first algorithm is intended to start with generation of an interaction graph followed by finding the longest path starting from the node with maximum degree. The second algorithm optimizes the number of SWAP gates between any pair of non-neighbouring qubits. Our proposed approach has a significant reduction in number of SWAP gates in 1D and 2D NTC architecture.

0 citations0 reviewsNo code linkedOpen access
preprint2020arXiv

The Blockchain Based Auditor on Secret key Life Cycle in Reconfigurable Platform

The growing sophistication of cyber attacks, vulnerabilities in high computing systems and increasing dependency on cryptography to protect our digital data make it more important to keep secret keys safe and secure. Few major issues on secret keys like incorrect use of keys, inappropriate storage of keys, inadequate protection of keys, insecure movement of keys, lack of audit logging, insider threats and non-destruction of keys can compromise the whole security system dangerously. In this article, we have proposed and implemented an isolated secret key memory which can log life cycle of secret keys cryptographically using blockchain (BC) technology. We have also implemented a special custom bus interconnect which receives custom crypto instruction from Processing Element (PE). During the execution of crypto instructions, the architecture assures that secret key will never come in the processor area and the movement of secret keys to various crypto core is recorded cryptographically after the proper authentication process controlled by proposed hardware based BC. To the best of our knowledge, this is the first work which uses blockchain based solution to address the issues of the life cycle of the secret keys in hardware platform. The additional cost of resource usage and timing complexity we spent to implement the proposed idea is very nominal. We have used Xilinx Vivado EDA tool and Artix 7 FPGA board.

0 citations0 reviewsNo code linkedOpen access