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Paper detail

Status of the QPACE Project

We give an overview of the QPACE project, which is pursuing the development of a massively parallel, scalable supercomputer for LQCD. The machine is a three-dimensional torus of identical processing nodes, based on the PowerXCell 8i processor. The nodes are connected by an FPGA-based, application-optimized network processor attached to the PowerXCell 8i processor. We present a performance analysis of lattice QCD codes on QPACE and corresponding hardware benchmarks.

preprint2008arXivOpen access
H. BaierH. BoettigerM. DrochnerN. EickerU. FischerZ. FodorG. GoldrianS. HeybrockD. HierlT. HuthB. KrillJ. LauritsenT. LippertT. MaurerJ. McFaddenN. MeyerA. NobileI. OudaM. PivantiD. PleiterA. SchäferH. SchickF. SchifanoH. SimmaS. SolbrigT. StreuerK. H. SulankeR. TripiccioneT. WettigF. Winter
hep-lat
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H. BaierH. BoettigerM. DrochnerN. EickerU. FischerZ. FodorG. GoldrianS. HeybrockD. HierlT. HuthB. KrillJ. LauritsenT. LippertT. MaurerJ. McFaddenN. MeyerA. NobileI. OudaM. PivantiD. PleiterA. SchäferH. SchickF. SchifanoH. SimmaS. SolbrigT. StreuerK. H. SulankeR. TripiccioneT. WettigF. Winter

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