A Comparison of CPU and GPU implementations for the LHCb Experiment Run 3 Trigger

preprint2022arXivOpen access
R. AaijM. AdinolfiS. AiolaS. AkarJ. AlbrechtM. AlexanderS. AmatoY. AmhisF. ArchilliM. BalaG. BassiL. BianM. P. BlagoT. BoettcherA. BoldyrevS. BorghiA. Brea RodriguezL. CaleficeM. Calvo GomezD. H. Cámpora PérezA. CardiniM. CattaneoV. ChobanovaG. CiezarekX. Cid VidalJ. L. CobbledickJ. A. B. CoelhoT. ColomboA. ContuB. CouturierD. C. CraikR. CurrieP. d'ArgentM. De CianD. DerkachF. DordeiM. DorigoL. DufourP. DuranteA. DziurdaA. DzyubaS. EasoS. EsenP. Fernandez DeclaraS. FilippovC. FitzpatrickM. FrankP. GandiniV. V. GligorovE. GolobardesG. GrazianiL. GrilloP. A. GüntherS. Hansmann-MenzemerA. M. HennequinL. HenryD. HillS. E. HollittJ. HuW. HulsbergenR. J. HunterM. HushchynB. K. JashalC. R. JonesS. KlaverK. KlimaszewskiR. KopecnaW. KrzemienM. KucharczykR. LaneF. LazzariR. Le GacP. LiJ. H. LopesM. Lucio MartinezA. LupatoO. LuptonX. LyuF. MachefertO. MadejczykS. MaldeJ. F. MarchandS. MarianiC. Marin BenitoD. Martinez SantosF. Martinez VidalR. MatevM. MazurekB. MitreskaD. S. MitzelM. J. MorelloH. MuP. MuzzettoP. NaikM. NeedhamN. NeriN. NeufeldN. S. NolteD. O'HanlonA. OyangurenM. Pepe AltarelliS. PetrucciM. PetruzzoL. PicaF. PisaniA. PiucciF. PolciA. PoluektovE. PolycarpoC. ProuveG. PunziR. QuaglianiR. I. Rabadan TrejoM. Ramos PernasM. S. RangelF. RatnikovG. RavenF. ReissV. RenaudinP. RobbeA. RyzhikovM. SantimariaM. SaurM. SchillerR. SchwemmerB. SciasciaA. SolominF. SuljikN. SkidmoreM. D. SokoloffP. SpradlinM. StahlS. StahlH. StevensL. SunA. SzabelskiT. SzumlakM. SzymanskiD. Y. TouG. TuciA. UsachovN. Valls CanudasR. Vazquez GomezS. VecchiM. VesterinenX. Vilasis-CardonaD. vom BruchZ. WangT. WojtonM. WhiteheadM. WilliamsM. WitekY. XieA. XuH. YinM. ZdybalO. ZenaievD. ZhangL. ZhangX. Zhu

Abstract

The LHCb experiment at CERN is undergoing an upgrade in preparation for the Run 3 data taking period of the LHC. As part of this upgrade the trigger is moving to a fully software implementation operating at the LHC bunch crossing rate. We present an evaluation of a CPU-based and a GPU-based implementation of the first stage of the High Level Trigger. After a detailed comparison both options are found to be viable. This document summarizes the performance and implementation details of these options, the outcome of which has led to the choice of the GPU-based implementation as the baseline.

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