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Jiading Gai

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2 publications

preprint2026arXiv

DualKV: Shared-Prompt Flash Attention for Efficient RL Training with Large Rollouts and Long Contexts

Modern RL post-training methods such as GRPO and DAPO train on NN response sequences of RR tokens sampled from a shared prompt of PP tokens, but standard FlashAttention replicates all PP prompt tokens NN times across both forward and backward passes -- duplicating compute and memory on identical hidden states. In large-rollout, long-context RL training (N≥16N{\geq}16, P≥8KP{\geq}8\text{K}), this redundancy dominates the policy update cost. We observe that in decoder-only models, causal masking makes prompt representations invariant across sequences at every layer, so all per-token operations (norms, projections, MLP) and attention can process the prompt once -- a property not yet exploited at the kernel level for training. We propose \textbf{DualKV}, the first FlashAttention kernel variant that eliminates shared-prompt replication during RL training, via (1)~fused CUDA forward and backward kernels that iterate over two disjoint KV regions -- shared context and per-sequence response -- in a single kernel launch, and (2)~a data-pipeline redesign in veRL that repacks N(P+R)N(P{+}R) tokens into P+NRP{+}NR tokens per micro-batch, extending the token reduction from attention to the entire model by a factor ρ=N(P+R)/(P+NR)ρ= N(P{+}R)/(P{+}NR). DualKV is mathematically equivalent to standard attention and introduces no approximation. On Qwen3-8B GRPO training with 8×\timesH100 GPUs (N=32N{=}32, 8K-context), DualKV achieves 1.631.63--2.09×2.09\times policy-update speedup, enables 2×2\times larger micro-batches, and raises MFU from 36%36\% to 76%76\%. Similar gains hold for DAPO (2.47×2.47\times speedup, 77%77\% MFU). At 30B MoE scale on 16×\timesH100, DualKV achieves 3.82×3.82\times policy-update and 3.38×3.38\times end-to-end step speedup over FlashAttention (which requires 4-way Ulysses sequence parallelism to avoid OOM).

preprint2020arXiv

Optimizing Memory-Access Patterns for Deep Learning Accelerators

Deep learning (DL) workloads are moving towards accelerators for faster processing and lower cost. Modern DL accelerators are good at handling the large-scale multiply-accumulate operations that dominate DL workloads; however, it is challenging to make full use of the compute power of an accelerator since the data must be properly staged in a software-managed scratchpad memory. Failing to do so can result in significant performance loss. This paper proposes a systematic approach which leverages the polyhedral model to analyze all operators of a DL model together to minimize the number of memory accesses. Experiments show that our approach can substantially reduce the impact of memory accesses required by common neural-network models on a homegrown AWS machine-learning inference chip named Inferentia, which is available through Amazon EC2 Inf1 instances.

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