Paper detail

Suppression of Conductance in a Topological Insulator Nanostep Junction

We investigate quantum transport via surface states in a nanostep junction on the surface of a 3D topological insulator that involves two different side surfaces. We calculate the conductance across the junction within the scattering matrix formalism and find that as the bias voltage is increased, the conductance of the nanostep junction is suppressed by a universal factor of 1/3 compared to the conductance of a similar planar junction based on a single surface of a topological insulator. We also calculate and analyze the Fano factor of the nanostep junction and predict that the Fano factor saturates at 1/5, five times smaller than for a Poisson process.