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Simulation of temperature profile for the electron- and the lattice-systems in laterally structured layered conductors

Electrons in operating microelectronic semiconductor devices are accelerated by locally varying strong electric field to acquire effective electron temperatures nonuniformly distributing in nanoscales and largely exceeding the temperature of host crystal lattice. The thermal dynamics of electrons and the lattice are hence nontrivial and its understanding at nanoscales is decisively important for gaining higher device performance. Here, we propose and demonstrate that in layered conductors nonequilibrium nature between the electrons and the lattice can be explicitly pursued by simulating the conducting layer by separating it into two physical sheets representing, respectively, the electron- and the lattice-subsystems. We take, as an example of simulating GaAs devices, a 35nm thick 1um wide U-shaped conducting channel with 15nm radius of curvature at the inner corner of the U-shaped bend, and find a remarkable hot spot to develop due to hot electron generation at the inner corner. The hot spot in terms of the electron temperature achieves a significantly higher temperature and is of far sharper spatial distribution when compared to the hot spot in terms of the lattice temperature. Similar simulation calculation made on a metal (NiCr) narrow lead of the similar geometry shows that a hot spot shows up as well at the inner corner, but its strength and the spatial profiles are largely different from those in semiconductor devices. The remarkable difference between the semiconductor and the metal is interpreted to be due to the large difference in the electron specific heat, rather than the difference in the electron phonon interaction. This work will provide useful hints to deeper understanding of the nonequilibrium properties of electrical conductors, through a simple and convenient method for modeling nonequilibrium layered conductors.