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High-level synthesis under I/O Timing and Memory constraints

The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm.

preprint2006arXivOpen access
Philippe CoussyGwenolé CorrePierre BomelEric SennEric Martin
Hardware Architecture
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Open access5 authors1 topic
Imported metadata coverageMissing code, dataset, citation and institution fields are tracked without dominating the paper.Details
Citations: 0Reviews: 0Saves: 0Code: not linkedDataset: not linkedInstitutions: 0

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Philippe CoussyGwenolé CorrePierre BomelEric SennEric Martin

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