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Paper detail

Evaluation of SystemC Modelling of Reconfigurable Embedded Systems

This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze VanillaNet Platform running MicroBlaze uClinux operating system. The paper compares Register Transfer Level (RTL) Hardware Description Language (HDL) simulation speed to the simulation speed of several different SystemC models. It is shown that simulation speed of pin and cycle accurate models can go up to 150 kHz, compared to 100 Hz range of HDL simulation. Furthermore, utilising techniques that temporarily compromise cycle accuracy, effective simulation speed of up to 500 kHz can be obtained.

preprint2007arXivOpen access
Tero RissaAdam DonlinWayne Luk
Hardware Architecture
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Tero RissaAdam DonlinWayne Luk

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