Abstract
A promising architecture for scaling up quantum computers based on trapped ions are so called Quantum Charged-Coupled Devices (QCCD). These consist of multiple ion traps, each designed for solving specific tasks, that are connected by transport links. In this paper we present the backend compiler phases needed for running quantum circuits on a QCCD architecture, while providing strategies to solve the optimization problems that occur when generating assembly instructions. We implement and test these strategies for the QVLS-Q1 chip architecture.
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