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A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators

Barriers that prevent programmers from using FPGAs include the need to work within vendor specific CAD tools, knowledge of hardware programming models, and the requirement to pass each design through synthesis, place and route. In this work, a dynamic overlay is designed to support Just- In-Time assembly by composing hardware operators to construct full accelerators. The hardware operators are pre-synthesized bit- streams and can be downloaded to Partially Reconfigurable(PR) regions at runtime.

preprint2016arXivOpen access
Zeyad AklahSen MaDavid Andrews
Hardware Architecture
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Open access3 authors1 topic
Imported metadata coverageMissing code, dataset, citation and institution fields are tracked without dominating the paper.Details
Citations: 0Reviews: 0Saves: 0Code: not linkedDataset: not linkedInstitutions: 0

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Zeyad AklahSen MaDavid Andrews

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